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SQPU256: The whole stack. Engineered as one.

Chip to cryostat. Control to code. Advay Labs is building every layer of a 256-qubit superconducting quantum processor, and proving it one measured milestone at a time.

SQPU256

Our flagship quantum processor programme

256 superconducting qubits, engineered as a complete system, not just a chip.

Tile-1 → 16 → 64 → 256

Earned, one scale at a time

Every stage closes its risks before the next begins.

Seven layers

Processor to runtime

Every layer, engineered as one.

Tvarit

Digital engineering layer

Measured data in. Better design out.

The flagship programme

One processor. Every layer behind it.

SQPU256 is what we're building. The full system is how we get there. From qubit design to workload mapping, Advay engineers each layer together, on one programme, along one evidence-gated path to scale.

01 · Processor programme

SQPU256

The flagship superconducting quantum processor target and the integrated system architecture required to control, calibrate and operate it.

02 · Hardware progression

Measured milestones

SQPU Tile-1, SQPU16 and SQPU64 are structured as learning stages toward SQPU256, with explicit technical questions and exit evidence.

03 · Research ecosystem

Defined collaboration interfaces

Advay engages laboratories, foundries, packaging and cryogenic teams, RF-control specialists, researchers and institutions through scoped technical workstreams.

SQPU256 AT A GLANCE

An architecture built to learn at every scale.

The figures below describe scope, progression and method. Advay does not publish coherence, fidelity, gate-speed or yield numbers for a device that has not yet been fabricated and measured.

  • ✓Target scale: 256 superconducting qubits.
  • ✓Hardware progression: SQPU Tile-1 → SQPU16 → SQPU64 → SQPU256.
  • ✓System scope: processor, package, cryogenics, microwave control, readout, calibration and software interfaces.
  • ✓Engineering focus: frequency planning, coupler behaviour, readout organisation, crosstalk, yield, package parasitics and repeatable calibration.
  • ✓Development method: evidence-gated advancement from design and simulation to fabrication and measurement.

Why we build this way

Learn first. Then scale.

Every stage has to teach us what the hardware can really do before we take the next step. Simulation guides us. Measurement proves us right or wrong.

A processor is more than a qubit count

Scalable operation depends on device behaviour, package modes, control-channel density, calibration repeatability, readout organisation and software mapping working together.

Scale must follow measured learning

Moving directly to a larger architecture can multiply unresolved process, frequency, packaging and control risks. Advay uses intermediate hardware milestones to close them deliberately.

Claims must remain evidence-bound

Designed, simulated and projected results are useful, but they are not measured hardware performance. Every public statement must preserve that distinction.

Measured development programme

From first hardware learning to the SQPU256 target.

SQPU Tile-1, SQPU16 and SQPU64 are not separate products. They are controlled stages for closing the technical risks that determine whether the flagship architecture can scale credibly.
stage 0underway

Architecture and partner closure

Define the design basis, public-safe interfaces, process assumptions, evidence gates and the route to fabrication and measurement.

01
stage 1planned

SQPU Tile-1

A first measured hardware-learning milestone intended to compare engineering assumptions with physical device, package, cryogenic and control behaviour.

02
stage 2planned

SQPU16

An intermediate scale intended to establish repeatable multi-qubit integration and calibration learning.

03
stage 3future

SQPU64

A system-scaling stage intended to stress integration, control density, readout organisation, calibration automation and operating stability.

04
stage 4future

SQPU256

The flagship target that consolidates measured design rules, manufacturing learning and integrated system methods from earlier stages.

05

Research and engineering partners

Let's solve the hard parts together.

Nobody builds a quantum computer alone. We team up with experts who know one layer deeply, working on a focused question with a clear goal and results we can measure.

Foundries and process partners

Process review, test structures, design-for-manufacture feedback and controlled layout handoff, within an agreed confidentiality boundary.

Packaging and cryogenic facilities

Package concepts, shielding and thermalisation, interconnect design, cooldown access and measurement time on qualified cryogenic systems.

Microwave control and instrumentation

Signal generation and acquisition, amplification, filtering, channel scaling and the control-electronics interfaces an operable system depends on.

Measurement and calibration groups

Characterisation campaigns, automated calibration methods, drift and repeatability studies, and disciplined model reconciliation.

Universities and research groups

Joint research, student and doctoral projects, benchmark methodology, technical notes and co-authored publications with defined scope.

Institutional and national programmes

Long-horizon capability building where facilities, talent, research and hardware milestones need to be planned as one programme.

Enabling engineering layer

Tvarit supports the SQPU programme; it does not define the company.

Tvarit is Advay’s digital engineering environment for circuit analysis, architecture mapping, simulation, resource projection, noise sensitivity and evidence-labelled reporting. Outputs remain simulated or projected unless explicitly linked to measured hardware data.

  • ✓OpenQASM circuit analysis and ideal execution.
  • ✓Architecture mapping and resource projection.
  • ✓Noise, sensitivity and reference-profile analysis.
  • ✓Evidence-labelled reports and API workflows.

Research integrity

Know what's real, at a glance.

Every result we publish carries a label showing how far it has come, from designed on paper to measured on real hardware. Targets stay targets. Simulations stay simulations.
Designed
Simulated
Projected
Fabricated
Measured
Independently reviewed

Institutional and strategic programmes

Some collaborations are larger than a single workstream.

Building superconducting quantum hardware requires facilities, fabrication access, cryogenic capacity, instrumentation, specialist people and sustained multi-year commitment. Where a partner wants to shape that programme rather than contribute to one part of it, Advay engages through a structured, confidential technical and programme review.

  • ✓A defined technical objective and the hardware milestone it maps to.
  • ✓The capability each side contributes — facilities, process access, instrumentation, people or programme resourcing.
  • ✓Evidence gates, review points and what constitutes completion for each stage.
  • ✓Confidentiality, publication rights and intellectual-property boundaries agreed before technical material is exchanged.

Frequently asked

Clear answers about the SQPU programme.

Advay Labs is developing SQPU256, a 256-qubit superconducting quantum processor target, together with the packaging, cryogenic, microwave-control, calibration and software interfaces required to operate it as an integrated system.

Hardware collaboration

Help advance the next measured milestone.

Start a defined conversation around research, fabrication, packaging, cryogenics, RF control, calibration, institutional capability or a long-horizon programme partnership.