Research at Advay Labs

Researching the engineering required to scale superconducting quantum systems.

Advay’s research programme connects device and microwave engineering, packaging, cryogenic control, calibration, error correction and compiler behaviour around the SQPU architecture.

Research themes

Six connected questions, from physical device to workload mapping.

Each theme is stated at a level a specialist can evaluate. Specific designs, process parameters, datasets and partner work remain subject to the relevant confidentiality and publication arrangements.

Superconducting devices and process variation

How junction and film process behaviour propagates into device parameters, and how that variation is anticipated rather than discovered after fabrication.

Couplers, connectivity and frequency allocation

How coupling structures and frequency plans interact with connectivity choices, collision risk and the yield of a usable device.

Resonators, electromagnetic extraction and package modes

How readout structures, electromagnetic behaviour and package modes shape what a fabricated device can actually deliver in a cryostat.

Cryogenic control, readout and calibration

How signal delivery, acquisition, channel density and calibration effort scale as qubit count grows, and what breaks first when they do not.

Error correction and logical-resource analysis

What physical resources a given code and error budget imply — reported as projection, never as achieved logical performance.

Compiler–hardware co-design and workload mapping

How decomposition, routing, scheduling and calibration-aware mapping change once real architectural constraints replace idealised assumptions.

Research outputs

Publish evidence that researchers can inspect, reproduce and cite.

As content becomes available, this section should host peer-reviewed publications, preprints, technical notes, benchmark methods, architecture briefs, public-safe measurement summaries, datasets where appropriate and reproducible examples. Categories should appear only when real material exists.

Methods and technical notes

Clearly scoped documents describing the question, method, configuration, assumptions, uncertainty, limitations and evidence class.

Benchmarks and reproducible examples

Versioned circuits, reference profiles, analysis settings and bounded outputs that can be independently inspected.

Measurement summaries

Public-safe physical results with test conditions and uncertainty, without disclosing proprietary implementation details.

Research integrity

Designed, Simulated, Projected, Fabricated, Measured and Independently Reviewed.

Every result should state the system configuration, method, assumptions, uncertainty, limitations and evidence class. Simulation is not presented as physical measurement, and target performance is not presented as achieved performance.

Designed

Architecture or engineering intent

A defined design basis or implementation plan that has not yet been physically realised.

Simulated

Computed under a declared model

A result produced by specified software, assumptions, parameters and numerical methods.

Projected

Model-based extrapolation

An estimate derived from stated assumptions, reference profiles or scaling models.

Fabricated

Physical artefact produced

A device, test structure, package or related component exists, without implying successful operation.

Measured

Observed on physical hardware

Data was collected from a physical setup with configuration, method, uncertainty and limitations recorded.

Independently Reviewed

External technical review

A qualified external party reviewed the defined artefact, method or evidence within an explicit scope.

Collaboration models

Structured work with clear technical boundaries.

Collaboration may include joint research, device or package review, fabrication and process learning, measurement campaigns, calibration and control integration, benchmark design, student projects, publications and institutional capability programmes.