Hardware development programme

Measured milestones from first hardware learning to SQPU256.

Advay’s programme is structured to close the highest-risk device, fabrication, packaging, cryogenic, control and calibration questions before increasing system scale. Public descriptions remain high-level; detailed acceptance criteria and proprietary implementation data are controlled.

Programme path

One flagship architecture, advanced through evidence-gated stages.

The stages describe intended technical learning, not guaranteed dates or achieved hardware performance. Their status must be maintained against factual programme evidence.

stage 0underway

Architecture and partner closure

Define the design basis, public-safe interfaces, process assumptions, evidence gates and the route to fabrication and measurement.

stage 1planned

SQPU Tile-1

A first measured hardware-learning milestone intended to compare engineering assumptions with physical device, package, cryogenic and control behaviour.

stage 2planned

SQPU16

An intermediate scale intended to establish repeatable multi-qubit integration and calibration learning.

stage 3future

SQPU64

A system-scaling stage intended to stress integration, control density, readout organisation, calibration automation and operating stability.

stage 4future

SQPU256

The flagship target that consolidates measured design rules, manufacturing learning and integrated system methods from earlier stages.

SQPU Tile-1

The first measured hardware-learning milestone.

Tile-1 is intended to compare key engineering assumptions with physical device and system behaviour at a controlled scale. The public website does not publish proprietary layouts, process parameters or unverified performance targets.

Design-to-fabrication learning

Confirm whether the selected design basis can be translated into foundry-reviewable structures under the agreed process and layout constraints.

System-integration learning

Observe package, cryogenic, RF-control, readout and instrumentation interactions that cannot be closed through chip design alone.

Model-reconciliation learning

Compare measured behaviour with the declared simulation and reference-profile assumptions, then update the next design stage.

Evidence gates

Advance only when the next decision is supported.

Each stage should produce a controlled evidence pack and a concise public-safe status. A stage moves forward when its acceptance questions have been reviewed and remaining risks are explicitly recorded.

Measured milestones from first hardware learning to SQPU256.

Programme path

One flagship architecture, advanced through evidence-gated stages.

Architecture and partner closure

SQPU Tile-1

SQPU16

SQPU64

SQPU256

SQPU Tile-1

The first measured hardware-learning milestone.

Design-to-fabrication learning

Confirm whether the selected design basis can be translated into foundry-reviewable structures under the agreed process and layout constraints.

System-integration learning

Observe package, cryogenic, RF-control, readout and instrumentation interactions that cannot be closed through chip design alone.

Model-reconciliation learning

Compare measured behaviour with the declared simulation and reference-profile assumptions, then update the next design stage.

Evidence gates

Advance only when the next decision is supported.

Before fabrication

Architecture basis, interfaces, test intent, process assumptions, design review and release controls.

After physical return

Fabrication record, package and assembly record, test configuration, cooldown and measurement evidence.

Before scaling

Characterisation, calibration, model reconciliation, unresolved risks, design changes and next-stage acceptance criteria.